Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device including a hollow structure around a semiconductor element.
Background Art
Multilayer wiring structures in which resin films and metal wires are repeatedly laminated on one another are used to achieve high integration and downsizing of semiconductor devices. However, the resin films cause parasitic capacitance to increase and cause electric characteristics of the semiconductor devices to deteriorate. In semiconductor devices including Y-type or T-type gate electrodes in particular, space under an overhang of the gate electrode is filled with resin, which increases the parasitic capacitance and causes the high-frequency gain to deteriorate (e.g., see T. Hisaka (1), H. Sasaki (1), T. Katoh (1), K. Kanaya (1), N. Yoshida (1), A. A. Villanueva (2), and J. A. del Alamo (2), IEICE Electronics Express, Vol. 7, No. 8, P. 558-562, (1) Mitsubishi Electric Corporation, (2) Massachusetts Institute of Technology).
In contrast, a method is proposed for forming a hollow structure around a semiconductor element by forming a sacrificial layer and a protective film on a semiconductor element and then removing the sacrificial layer (e.g., see Japanese Patent Application Laid-Open No. 2010-205837 and Japanese Patent Application Laid-Open No. 2011-049303).
Another method is proposed for forming a hollow structure between adjacent wires by laminating a sheet film on a substrate on which a plurality of wires are formed (e.g., see Japanese Patent Application Laid-Open No. 2003-142578). However, since there is no semiconductor element between wires, this method has nothing to do with a semiconductor device including a hollow structure around the semiconductor element.